Microelectronic devices, e.g., processors, memories, and other devices may be formed on a wafer that has multiple layers of integrated circuitry built on a silicon substrate. Typically, dielectric layers are deposited between the integrated circuitry layers of the wafer. The multiple integrated circuitry layers of the wafer may be connected through interconnect structures. For example, the interconnect structure may connect a copper line on one layer to the copper line on another layer of the wafer.
Currently, to improve bonding between the copper line and the upper dielectric layer, a single compressive dielectric layer is deposited between the copper line and the upper dielectric layer. Further, a selective electroless deposition of cobalt on the copper line may be used to improve adhesion between the copper line and the upper dielectric layer. The deposition of cobalt on the copper line is expensive and requires purchase and maintenance of an additional cobalt deposition tool.
The interface between the copper line and the upper dielectric layer, however, remains one of the weakest mechanical interfaces in interconnect structures and represents an easy path for crack generation, propagation and eventual mechanical failure.
Additionally, the poor bonding at the interface between the copper and the upper dielectric layer may enhance copper surface diffusion. The enhanced surface diffusion of copper along the copper/dielectric interface under an electric field (electromigration) results in a build up of a stress within the copper line that leads to de-bonding and eventual failure of the copper line.